The following relates to the operation of re-programmable non-volatile memory systems, such as semiconductor flash memory, and the management of such systems.
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retains its stored data even after power is turned off. Also, unlike ROM (read only memory), flash memory is rewritable similar to a disk storage device. In spite of the higher cost, flash memory is increasingly being used in mass storage applications.
Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions. Flash memory such as Flash EEPROM allows entire blocks of memory cells to be erased at the same time.
The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
In order to improve read and program performance, multiple charge storage elements or memory transistors in an array are read or programmed in parallel. Thus, a “page” of memory elements are read or programmed together. In existing memory architectures, a row typically contains several interleaved pages or it may constitute one page. All memory elements of a page are read or programmed together.
Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. For example, a nonvolatile memory cell may have a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
Non-volatile memory storage devices typically include a controller portion and a memory section and used a use logical-to-physical (L2P) mapping and use management tables for dynamic mapping. The logical-to physical mapping is performed by the controller and associates a physical address on the memory section where data is stored with a logical address by which a host identifies the data. In a standard arrangement, the management tables are stored in the non-volatile memory, but in order to provide high performance, management table copies are maintained also in the controller RAM, typically a DRAM. As the controller updates these tables during memory operations, the updated tables stored in the non-volatile device from time to time for synchronization, in an operation called Control Sync (CS).
If the system experiences an ungraceful shutdown (UGSD), such as losing power, any information updates made since the last control sync is lost, as this information was only held in volatile control memory. To avoid this problem, the system can operate in a blocking manner, where the flash controller does not send read/write commands to the flash dies, allowing them to complete their workload. Only after the workload is completed, confirmed and the control data is updated in the log are a new set of read/write commands sent. As the new block allocation will be performed according to the new log, data to control info coherency can be maintained, but at a loss of system performance due to the blocking.